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| PRELIMINARY Am79C873 NetPHYTM -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS s 100BASE-FX direct interface to industry standard electrical/optical transceivers s 10/100BASE-TX physical-layer, single-chip transceiver s Compliant with the IEEE 802.3u 100BASE-TX standard s Compliant with the ANSI X3T12 TP-PMD 1995 standard s Compliant with the IEEE 802.3u AutoNegotiation protocol for automatic link type selection s Supports the MII with serial management interface s Supports Full Duplex operation for 10 Mbps and 100 Mbps s High performance 100 Mbps clock generator and data recovery circuitry s Adaptive equalization circuitry for 100 Mbps receiver s Controlled output edge rates in 100 Mbps s Supports a 10BASE-T interface without the need for an external filter s Provides Loopback mode for system diagnostics s Includes flexible LED configuration capability s Digital clock recovery circuit using advanced digital algorithm to reduce jitter s Low-power, high-performance CMOS process s Available in a 100-pin PQFP package GENERAL DESCRIPTION The NetPHY-1 device is a physical-layer, single-chip, low-power transceiver for 100BASE-TX, 100BASE-FX, and 10BASE-T operations. On the media side, it provides a direct interface to Fiber Media for 100BASE-FX Fast Ethernet, Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the IEEE 802.3u Media Independent Interface (MII), the NetPHY-1 device connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors. The NetPHY-1 device uses a low-power, high-performance CMOS process. It contains the entire physical layer functions of 100BASE-FX and 100BASE-TX as defined by the IEEE 802.3u standard, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), 100BASE-TX Twisted Pair Physical Medium Dependent (TP-PMD) sublayer, and a 10BASE-T Encoder/Decoder (ENDEC). The NetPHY-1 device provides strong support for the Auto-Negotiation function utilizing automatic media speed and protocol selection. The NetPHY-1 device incorporates an internal wave-shaping filter to control rise/fall time, eliminating the need for external filtering on the 10/100 Mbps signals. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 22164 Rev: A Amendment/+2 Issue Date: February 1999 Refer to AMD's Website (www.amd.com) for the latest information. PRELIMINARY BLOCK DIAGRAM 25M OSCI LED1-4 TX CGM LED Driver PECL Driver FXTD 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver 100TXD Rise/Fall Time CTL 25M CLK 125M CLK MII Signals MII Interface/ Control 4B/5B Decoder Codegroup Alignment Descrambler Serial to Parallel NRZI to NRZ RX CRM MLT-3 to NRZI Adaptive EQ RXI Digital Logic PECL Receiver RX TX FXRD FXSD+ RXI 10TXD 10BASE-T Module Register Collision Detection Carrier Sense AutoNegotiation 22164A-1 2 Am79C873 PRELIMINARY CONNECTION DIAGRAM RPTR/NODE OPMODE3 10BTSER BPALIGN PHYAD4 PHYAD3 PHYAD1 PHYAD0 BP4B5B BPSCR TESTMODE 82 OPMODE2 OPMODE1 OPMODE0 PHYAD2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 DGND DVcc 85 84 83 AVcc FXSDFXSD+ FXRDFXRD+ AGND AVcc AVcc RXIRXI+ AGND AGND 10TXO10TXO+ AVcc AVcc AGND AGND FXTDFXTD+ AVcc AVcc AGND AGND 100TXO100TXO+ AVcc AVcc OSCI/X1 X2 81 RESET AGND AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RX_EN RX_ER/RXD4 RX_DV COL CRS RX_CLK DVcc DGND RXD0 RXD1 RXD2 RXD3 DVcc DGND MDIO MDC TX_CLK TX_EN DVcc DGND TXD0 TXD1 TXD2 TXD3 TX_ER/TXD4 TXLED RXLED LINKLED DGND COLLED Am79C873/KC NetPHY-1 RX_LOCK SPEED10 OSC/XTL LINKSTS CLK25M FDXLED TRIDRV BGREF BGRET AVcc DGND DGND DGND DGND DVcc AGND AGND DVcc UTP NC 22164A-2 Am79C873 3 PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C873 K C \W ALTERNATE PACKAGING OPTION \W = Trimmed and formed in a tray TEMPERATURE RANGE C = Commercial (0C to +70C) PACKAGE TYPE K = Plastic Quad Flat Pack (PQR100) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION Am79C873 NetPHY-1TM 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support Valid Combinations Valid Combinations Am79C873 KC\W Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 4 Am79C873 PRELIMINARY RELATED AMD PRODUCTS Part No. Controllers Am79C90 Description CMOS Local Area Network Controller for Ethernet (C-LANCETM) Integrated Controllers Am79C930 Am79C940 Am79C961A Am79C965A Am79C970A Am79C971 Am79C972 Am79C973/ Am79C975 Am79C978 PCnetTM-Mobile Single Chip Wireless LAN Media Access Controller Media Access Controller for Ethernet (MACETM) PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus PCnet-FAST Single-Chip Full Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support PCnet-Fast III Single-chip 10/100 Mbps PCI Ethernet Controller With Integrated PHY PCnet-Home Single-chip 1/10 Mbps PCI Home networking Controller Physical Layer Devices (Single-Port) Am7996 Am79761 Am79C98 Am79C100 IEEE 802.3/Ethernet/Cheapernet Transceiver Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHYTM-SD) Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) Physical Layer Devices (Multi-Port) Am79C871 Am79C988A Am79C989 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXrTM) Quad Integrated Ethernet Transceiver (QuIETTM) Quad Ethernet Switching Transceiver (QuESTTM) Integrated Repeater/Hub Devices Am79C981 Am79C982 Am79C983 Am79C984A Am79C985 Am79C987 Integrated Multiport Repeater Plus (IMR+) Basic Integrated Multiport Repeater (bIMR) Integrated Multiport Repeater 2 (IMR2TM) Enhanced Integrated Multiport Repeater (eIMRTM) Enhanced Integrated Multiport Repeater Plus (eIMR+TM) Hardware Implemented Management Information Base (HIMIBTM) Am79C873 5 PRELIMINARY CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device Configuration/Control/Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PHY Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 100BASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 100BASE Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4B5B Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 NRZ-to-NRZI Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PECL Driver For 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MLT-3 Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MLT-3 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 100BASE Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 100BASE-TX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 100BASE-FX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PECL Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MLT-3-to-NRZI Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 NRZI-to-NRZ Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Serial-to-Parallel Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Code Group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4B5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10BASE-T Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Collision Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MII Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Key to Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Basic Mode Control Register (BMCR) - Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Basic Mode Status Register (BMSR) - Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PHY ID Identifier Register 1 (PHYIDR1) - Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PHY Identifier Register 2 (PHYIDR2) - Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Auto-Negotiation Advertisement Register(ANAR) - Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5 . . . . . . . . . . . . . . . . . . . . 25 Auto-Negotiation Expansion Register (ANER) - Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AMD Specified Configuration Register (DSCR) - Register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AMD Specified Configuration and Status Register (DSCSR) - Register 17. . . . . . . . . . . . . . . . . 29 10BASE-T Configuration/Status (10BTCSRSCR) - Register 18 . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Am79C873 PRELIMINARY ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 MII 100BASE-TX Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MII 100BASE-TX Transmit Timing Parameters (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . 34 MII 100BASE-TX Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 MII-100BASE-TX Receive Timing Parameter (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . 35 Auto-Negotiation and Fast Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Auto-Negotiation and Fast Link Pulse Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MII 10BASE-T Nibble Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MII-10BASE-T Nibble Transmit Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MII 10BASE-T Receive Nibble Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MII-10BASE-T Receive Nibble Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10BASE-T SQE (Heartbeat) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10BASE-T Jab and Unjab Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MDIO Timing when OUTPUT by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MDIO Timing when OUTPUT by NetPHY-1 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MII Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MAGNETICS SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CRYSTAL SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 NETPHY-1 MII EXAMPLE SCHEMATIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Am79C873 7 PRELIMINARY PIN DESCRIPTIONS MII Interface TX_ER/TXD4 Transmit Error Input In 100 Mbps mode, if this signal is asserted high and TX_EN is active, the HALT symbol is substituted for the actual data nibble. In 10 Mbps mode, this input is ignored. In bypass modes (BP4B5B or BPALIGN), TX_ER becomes the TXD4 pin, the fifth TXD data bit. RXD[3:0] Receive Data Output/Z1 Nibble wide receive data (synchronous to RX_CLK - 25 MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK. In 10 Mbps serial mode, the RXD0 pin is used as the data output pin. RXD[3:1] are ignored. RX_CLK Receive Clock Output/Z1 Provides the recovered receive clock for different modes of operation: - 25 MHz nibble clock in 100 Mbps mode - 2.5 MHz nibble clock in 10 Mbps nibble mode - 10 MHz receive clock in 10 Mbps serial mode TXD[3:0] Transmit Data Input These are the transmit data input pins for nibble data from the MII in 100 Mbps or 10 Mbps nibble mode (25 MHz for 100 Mbps mode, 2.5 MHz for 10 Mbps nibble mode). In 10 Mbps serial mode, the TXD0 pin is used as the serial data input pin. TXD[3:1] are ignored. CRS Carrier Sense Output/Z1 This pin is asserted high to indicate the presence of carrier due to receive or transmit activities in 10BASET or 100BASE-TX Half Duplex modes. In Repeater, when Full Duplex or Loopback mode is a logic 1, it indicates the presence of carrier due only to receive activity. TX_EN Transmit Enable Input Active high input indicates the presence of valid nibble data on TXD[3:0] for both 100 Mbps or 10 Mbps nibble mode. In 10 Mbps serial mode, active high indicates the presence of valid 10 Mbps data on TXD0. COL Collision Detect Output/Z1 This pin is asserted high to indicate detection of collision conditions in 10 Mbps and 100 Mbps Half Duplexmodes. In 10BASE-T Half Duplex mode with Heartbeat set active (bit 13, register 18h), it is also asserted for a duration of approximately 1ms at the end of transmission to indicate heartbeat. In Full Duplex mode, this signal is always logic 0. There is no heartbeat function in Full Duplex mode. TX_CLK Transmit Clock Output/Z1 This pin provides the transmit clock output from the NetPHY-1 deviceas follows: - 25 MHz nibble transmit clock derived from transmit Phase Locked Loop (TX PLL) in 100BASE-TX mode - 2.5 MHz transmit clock in 10BASE-T nibble mode - 10 MHz transmit clock in 10BASE-T serial mode RX_DV Receive Data Valid Output/Z1 This pin is asserted high to indicate that valid data is present on RXD[3:0]. MDC Management Data Clock Input This pin is the synchronous clock to the MDIO management data input/output serial interface which is asynchronous to transmit and receive clocks. The maximum clock rate is 2.5 MHz. RX_ER/RXD4 Receive Error Output/Z1 This pin is asserted high to indicate that an invalid symbol has been detected inside a received packet in 100 Mbps mode. In a bypass mode (BP4B5B or BPALIGN modes), RX_ER becomes RXD4, the fifth RXD data bit of the 5B symbols. MDIO Management Data I/O Input/Output This pin is the bidirectional management instruction/ data signal that may be driven by the station management entity or the PHY. This pin requires a 1.5 K pullup resistor. 1. Goes to high impedance. 8 Am79C873 PRELIMINARY RX_EN Receive Enable Input This pin is active high enabled for receive signals RXD[3:0], RX_CLK, RX_DV and RX_ER. A low on this input tri-states these output pins. For normal operation in a NODE application, this pin should be pulled high. function will change to indicate the Polarity status for 10 Mbps operation. If polarity is inverted, the POLLED will go ON. COLLED Collision LED Output This pin indicates the presence of collision activity for 10 Mbps and 100 Mbps operation. This LED has no meaning for 10 Mbps or 100 Mbps Full Duplex operation (Active low). Media Interface RXI 100/10 Mbps-TX/T Twisted Pair Differential Input Pair Input These pins are the differential receive input for 10BASE-T and 100BASE-TX. They are capable of receiving 100BASE-TX MLT-3 or 10BASE-T Manchester encoded data. LINKLED (TRAFFIC LED) Link LED Output This pin indicates Good Link status for 10 Mbps and 100 Mbps operation (Active low). It functions as the TRAFFIC LED when bit 5 of register 16 is set to 1. In TRAFFIC LED mode, it is always ON when the link is OK. The TRAFFIC LED flashes when transmitting or receiving. FXRD 100BASE-FX PECL Differential Input Pair Input These pins are the differential receive input for 1 0 0 B A S E - F X . T h ey a r e c a p a bl e o f r e c e i v i n g 100BASE-FX. RXLED Receive LED Output Drain This pin indicates the presence of receive activity for 10 Mbps and 100 Mbps operation (Active low). The NetPHY-1 device incorporates a "monostable" function on the RXLED output. This ensures that even minimal receive activity will generate an adequate LED ON time. FXSD 100BASE-FX PECL Signal Detect Input These input signals from the FX-PMD transceiver indicate detection of a receive signal from the Fiber Media. 10TXO 10BASE-T Differential Output Pair Output This output pair provides controlled rise and fall times designed to filter the transmitters output. TXLED Transmit LED Output Drain This pin indicates the presence of transmit activity for 10 Mbps and 100 Mbps operation (Active low). The NetPHY-1 device incorporates a "monostable" function on the TXLED output. This ensures that even minimal transmit activity will generate an adequate LED ON time. 100TXO 100BASE-TX Twisted Pair Differential Output Pair Output This output pair drives MLT-3 encoded data to the 100 M twisted pair cable and provides controlled rise and fall times designed to filter the transmitters output, reducing any associated EMI. Device Configuration/Control/Status Interface UTP UTP Cable Indication Output This pin is the UTP Cable Indication. When UTP=1, it indicates that the UTP cable is being used. FXTD 100BASE-FX PECL Differential Output PairOutput These pins are the differential transmit output for 100BASE-FX. They are capable of transmitting 100BASE-FX SPEED10 Speed 10 Mbps Output When set high, this bit indicates a 10 Mbps operation, when set low 100 Mbps operation. This pin can drive a low current LED to indicate that 100 Mbps operation is selected. LED Interface These outputs can directly drive LEDs or provide status information to a network management device. FDXLED (POLLED) Polarity/Full Duplex LED Output This pin indicates Full Duplex mode status for 100 Mbps and 10 Mbps operation (Active low). If bit 4 of Register 16 (FDXLED_MODE) is set, the FDXLED pin RX_LOCK Lock for Clock/Data Recovery PLL Output When this pin is high, it indicates that the receiver recovery PLL logic has locked to the input data stream. Am79C873 9 PRELIMINARY LNKSTS Link Status Register Bit Output This pin reflects the status of bit 2 register 1. RTPR/NODE Repeater/Node Mode Input When set high, this bit selects REPEATER mode; when set low, it selects NODE. In REPEATER mode or NODE mode with Full Duplex configured, the Carrier Sense (CRS) output from the NetPHY-1 device will be asserted only during receive activity. In NODE mode or a mode not configured for Full Duplex operation, CRS will be asserted during receive or transmit activity. At power-up/reset, the value on this pin is latched into Register 16, bit 11. OPMODE0-OPMODE3 OPMODE0-OPMODE3 Input These pins are used to control the forced or advertised operating mode of the NetPHY-1 device (see table below). The value is latched into the NetPHY-1 device registers at power-up/rese.. OPOPOPOPMODE3 MODE2 MODE1 MODE0 Function Auto-Negotiation enable with all capabilities with Flow Control Auto-Negotiation enable without all capabilities without Flow Control Auto-Negotiation 100TX FDX with Flow Control only Auto-Negotiation 100TX FDX/HDX without Flow Control Auto-Negotiation 10TP FDX with Flow Control only Auto-Negotiation 10TX FDX/HDX without Flow Control Manual select 100TX FDX Manual select 100TX HDX Manual select 10TX FDX Manual select 10TX HDX Manual select 100FX FDX Manual select 100FX HDX Auto-Negotiation 10/100TX. HDX only BPALIGN Bypass Alignment Input This pin allows 100 Mbps transmit and receive data streams to bypass all of the transmit and receive operations when set high. At power-up/reset, the value on this pin is latched into bit Register 16, bit 13. 0 0 0 0 0 0 0 1 BP4B5B Bypass 4B5B Encoder/Decoder Input This pin allows 100 Mbps transmit and receive data streams to bypass the 4B to 5B encoder and 5B to 4B decoder circuits when set high. At power-up/reset, the value on this pin is latched into Register 16, bit 15. 0 0 1 0 BPSCR Bypass Scrambler/Descrambler Input This pin allows 100 Mbps transmit and receive data streams to bypass the scrambler and descrambler circuits when set high. At power-up/reset, the value on this pin is latched into Register 16, bit 14. 0 0 1 1 0 1 0 0 10BTSER Serial/Nibble Select 10 Mbps Serial Operation: Input 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 When set high, this input selects a serial data transfer mode. Manchester encoded transmit and receive data is exchanged serially with a 10 MHz clock rate on the least significant bits of the nibble-wide MII data buses, pin TXD[0] and RXD[0] respectively. This mode is intended for use with the NetPHY-1 device connected to a device (MAC or Repeater) that has a 10 Mbps serial interface. Serial operation is not supported in 100 Mbps mode. For 100 Mbps, this input is ignored. 10 and 100 Mbps Nibble Operation: When set low, this input selects the MII compliant nibble data transfer mode. Transmit and receive data is exchanged in nibbles on the TXD[3:0] and RXD[3:0] pins respectively. At power-up/reset, the value on this pin is latched into Register 18, bit 10. 1 1 1 1 10 Am79C873 PRELIMINARY Clock Interface OSCI/X1 Crystal or Oscillator Input Input This pin should be connected to a 25 MHz (50 ppm) crystal if OSC/XTL=0 or a 25 MHz (50 ppm) external TTL oscillator input, if OSC/XTLB=1. PHYAD4 PHY Address 4 Input This pin provides PHY address bit 4 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 4 during power up/reset. X2 Crystal Oscillator Output Output An external 25 MHz (50 ppm) crystal should be connected to this pin if OSC/XTL=0, or left unconnected if OSC/XTL=1. Miscellaneous NC No Connect These pins are to be left unconnected (floating). BGREF Bandgap Voltage Reference Input Connect a 6.01K , 1% resistor between this pin and the BGRET pin to provide an accurate current reference for the NetPHY-1 device. OSC/XTL Crystal or Oscillator Selector Pin Output OSC/XTL=0: An external 25 MHz (50ppm) crystal should be connected to X1 and X2 pins. s OSC/XTL=1: An external 25 MHz (50ppm) oscillator should be connected to X1 and X2 should be left unconnected. BGRET Bandgap Voltage Reference Return Input This is the return pin for 6.01K resistor connection. CLK25M 25 MHz Clock Output Output/Z This clock is derived directly from the crystal circuit. TRIDRV Tri-State Digital Output Input When set high, all digital output pins are set to a high impedance state, and I/O pins, go to input mode. PHY Address Interface The PHYAD[4:0] pins provide up to 32 unique PHY addresses. An address selection of all zeros (00000) will result in a PHY isolation condition. See the isolate bit description in the BMCR, address 00. RESET Reset Input This pin is the active low input that initializes the NetPHY1 device. It should remain low for 30 ms after VCC has stabilized at 5 Vdc (nominal) before it transitions high. PHYAD0 PHY Address 0 Input This pin provides PHY address bit 0 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 8 during power up/reset. TESTMODE Test Mode Control Pin TESTMODE=0: Normal operating mode. TESTMODE=1: Enable test mode. Input PHYAD1 PHY Address 1 Input This pin provides PHY address bit 1 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 7 during power up/reset. Power and Ground Pins The power (VCC) and ground (GND) pins of the NetPHY-1 device are grouped in pairs of two categories Digital Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair. PHYAD2 PHY Address 2 Input This pin provides PHY address bit 2 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 6 during power up/reset. DGND Digital Logic Ground These pins are the digital supply pairs. Power DVCC Digital Logic Power Supply These pins are the digital supply pairs. Power PHYAD3 PHY Address 3 Input This pin provides PHY address bit 3 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 5 during power up/reset. AGND Analog Circuit Ground Power These pins are the analog circuit supply pairs. AVCC Analog Circuit Power Supply Power These pins are the analog circuit supply pairs. Am79C873 11 PRELIMINARY FUNCTIONAL DESCRIPTION The NetPHY-1 Fast Ethernet single-chip transceiver, provides the functionality as specified in the IEEE 802.3u standard, integrates complete 100BASE-FX, 100BASE-TX modules and a complete 10BASE-T module. The NetPHY-1 device provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The NetPHY-1 device performs all Physical Coding Sublayer (PCS), Physical Media Access (PMA), Twisted Pair Physical Medium Dependent (TP-PMD) sublayer, 10BASE-T Encoder/Decoder, and Twisted Pair Media Access Unit (TPMAU) functions. Figure 1 shows the major functional blocks implemented in the NetPHY-1 device. 100Base Transmitter 100Base Receiver MII Interface 10Base-T Tranceiver Carrier Sense Collision Detection Auto Negotiation MII Serial Management Interface 22164A-3 Figure 1. Functional Block Diagram MII Interface The purpose of the MII interface is to provide a simple, easy to implement connection between the MAC Reconciliation layer and the PHY. The MII is designed to make the differences between various media transparent to the MAC sublayer. The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the PHY and the Reconciliation layer. s TXD (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to TX_CLK. For each TX_CLK period which TX_EN is asserted, TXD (3:0) are accepted for transmission by the PHY. s TX_CLK (transmit clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the TX_EN, TXD, and TX_ER signals. s TX_EN (transmit enable) input from the MAC reconciliation sublayer to indicate nibbles are being presented on the MII for transmission on the physical medium. TX_ER (transmit coding error) transitions synchronously with respect to TX_CLK. If TX_ER is asserted for one or more clock periods, and TX_EN is asserted, the PHY will emit one or more symbols that are not part of the valid data delimiter set somewhere in the frame being transmitted. s RXD (receive data) is a nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to RX_CLK. For each RX_CLK period which RX_DV is asserted, RXD (3:0) are transferred from the PHY to the MAC reconciliation sublayer. s RX_CLK (receive clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the RX_DV, RXD, and RX_ER signals. 12 Am79C873 PRELIMINARY s RX_DV (receive data valid) input from the PHY to indicate the PHY is presenting recovered and decoded nibbles to the MAC reconciliation sublayer. To interpret a receive frame correctly by the reconciliation sublayer, RX_DV must encompass the frame starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter. s RX_ER (receive error) transitions synchronously with respect to RX_CLK. RX_ER will be asserted fo r 1 o r m o r e c l o ck p e r i o d s t o i n d i c a t e t o the reconciliation sublayer that an error was detected somewhere in the frame being transmitted from the PHY to the reconciliation sublayer. s CRS (carrier sense) is asserted by the PHY when either the transmit or receive medium is non-idle and deasserted by the PHY when the transmit and receive medium are idle. Figure 2 depicts the behavior of CRS during 10BASE-T and 100BASE-TX transmission. TXD IDLE SSD J/K Preamble SFD Data ESD T/R IDLE CRS 100Base-TX TXD Preamble SFD Data EFD CRS 10Base-T 22164A-4 Figure 2. Carrier Sense during 10BASE-T and 100BASE-TX Transmission 100BASE Operation The 100BASE transmitter receives 4-bit nibble data clocked in at 25 MHz at the MII and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100 Mbps. The on-chip clock circuit converts the 25 MHz clock into a 125 MHz clock for internal use. The IEEE 802.3u specification defines the Media Independent Interface. The interface specification defines a dedicated receive data bus and a dedicated transmit data bus. These two busses include various controls and signal indications that facilitate data transfers between the NetPHY-1 device and the Reconciliation layer. 100BASE Transmit The 100BASE transmitter consists of the functional blocks shown in Figure 3. The 100BASE transmit section converts 4-bit synchronous data provided by the MII to a scrambled MLT-3 125 million symbols per second serial data stream. Am79C873 13 PRELIMINARY 25M OSCI LED1-4# TX CGM LED Driver PECL Driver FXTD 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver 100TXD Rise/Fall Time CTL MII Signals MII Interface/ Control 10BASE-T Module RX TX RXI 10TXD Register Collision Detection Carrier Sense AutoNegotiation 22164A-5 Figure 3. 100BASE Transmitter Functional Block Diagram The block diagram in Figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: s 4B5B Encoder s Scrambler s Parallel-to-Serial Converter s NRZ-to-NRZI Converter s PECL Driver (For FX Operation) s NRZI to MLT-3 (For TX Operation) s MLT-3 Driver (For TX Operation) combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code-group pair (01101 00111) indicating end of frame. After the T/R code-group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The NetPHY-1 device includes a Bypass 4B5B conversion option within the 100BASE-TX transmitter for support of applications like 100 Mbps repeaters which do not require 4B5B conversion. 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission (see Table 1). This conversion is required for control and packet data to be 14 Am79C873 PRELIMINARY Table 1. Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H V V V V V V V V V V 4B5B Code Group 4B code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Meaning Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Idle SFD (1) SFD (2) ESD (1) ESD (2) Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid the twisted pair cable in 100BASE-TX operation. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. Since EMI is not a concern in a fiber application, the scrambler is bypassed in 100BASE-FX. Parallel-to-Serial Converter The Parallel-to-Serial Converter receives parallel 5B scrambled data from the scrambler and serializes it (i.e., converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ-to-NRZI Encoder block NRZ-to-NRZI Converter After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100BASE-TX transmission over Category-5 unshielded twisted pair cable. PECL Driver For 100BASE-FX The PECL driver accepts NRZI coded data and converts it to PECL signal levels for transmission over fiber media. The output pair is a differential pseudo ECL (PECL) interface designed to connect directly to a standard fiber optic PMD. The differential driver for the FXTD is current mode and is designed to drive resistive termination in a complementary mode. The FXTD pins are incapable of sourcing current, this implies that VOH must be set by the ratios of the Thevenin termination resistors for each of the lines. RIOH is a pull-up resistor connected from the FXTD output to VCC. RIOL is a pulldown resistor connected from the FXTD output to ground. RIOH and RIOL are electrically in parallel from an AC standpoint. A target impedance of 50 is needed for the transmission line impedance. A value of 62 for RIOH and a value of 300 for RIOL will yield a Thevenin equivalent characteristic impedance of 49.7 and a VOH value of VCC-.88 volts, compatible with PECL circuits. VOL is required to be VDD-1.81 or greater. A sink current of 19 milli-amps (mA) would achieve this through the output termination resistors. MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. Scrambler The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on Am79C873 15 PRELIMINARY MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current MLT-3 signal. Refer to Figure 4 for the block diagram of the MLT-3 converter. s Signal Detect s Adaptive Equalization s MLT-3-to-Binary Decoder s Clock Recovery Module s NRZI -o-NRZ Decoder s Serial-to-Parallel Converter s Descrambler s Code Group Alignment s 4B5B Decoder 100BASE-TX Signal Detect The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100BASE-TX standards for both voltage thresholds and timing parameters. 100BASE Receiver The 100BASE receiver contains several function blocks that convert the scrambled 125 Mbps serial data to synchronous 4-bit nibble data that is then provided to the MII. The receive section contains the following functional blocks: D CK Binary In Q Q Binary plus Binary minus Common Driver MLT-3 Binary In MLT-3 22164A-6 Figure 4. MLT-3 Converter Block Diagram 100BASE-FX Signal Detect The NetPHY-1 device accepts signal detect information on the FXSD pin at PECL signal levels from the FX Optical Module. Adaptive Equalization When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will 16 Am79C873 PRELIMINARY cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. PECL Receiver The PECL receiver accepts PECL signal-level data from the FX Optical Module and presents it to the Clock Recovery Module. MLT-3-to-NRZI Decoder The NetPHY-1 device decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relationship between NRZI and MLT-3 data is shown in Figure 4. Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3-to-NRZI decoder or the PECL Receiver. The Clock Recovery Module locks onto the data stream and extracts the 125 MHz reference clock. The extracted and synchronized clock and data are presented to the NRZI-to-NRZ Decoder. NRZI-to-NRZ Decoder The transmit data stream is required to be NRZI encoded in for compatibility with 100BASE transmission over. This conversion process must be reversed on the receive end. The NRZI-to-NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block. Serial-to-Parallel Converter The Serial-to-Parallel Converter receives a serial data stream from the NRZI-to-NRZ converter, and converts the data stream to parallel data to be presented to the descrambler. Descrambler Because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block. 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first two 5-bit code groups received are the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R symbols).The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer. 10BASE-T Operation The 10BASE-T transceiver is IEEE 802.3u compliant. When the NetPHY-1 device is operating in 10BASE-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted into nibble format for presentation to the MII interface. Collision Detection For Half Duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. When a collision has been detected, it will be reported by the COL signal on the MII interface. Collision detection is disabled in Full Duplex operation. Carrier Sense Carrier Sense (CRS) is asserted in Half Duplex operation during transmission or reception of data. During Full Duplex mode, CRS is asser ted only during receive operations. Auto-Negotiation The objective of Auto-Negotiation is to provide a means to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Auto-Negotiation does not test the link segment characteristics. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. Auto-Negotiation also provides a parallel detection function for devices that do not support the Auto-Negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined. If it is discovered that the signal matches a technology that the receiving device Note: The scrambler is bypassed for 100BASE-FX operation. Code Group Alignment The Code Group Alignment block receives unaligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed boundary. Am79C873 17 PRELIMINARY supports, a connection will be automatically established using that technology. This allows devices that do not support Auto-Negotiation but support a common mode of operation to establish a link. MII Serial Management The MII serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. Through this interface it is possible to control and configure multiple PHY devices, get status and error information, and determine the type and capabilities of the attached PHY device(s). The NetPHY-1 devices management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, and 18. In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management registers. Serial Management Interface The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of Management Data Clock (MDC), and Management Data Input/Output (MDI/O) signals. The MDIO pin is bidirectional and may be shared by up to 32 devices. MDC MDIO Read 32 "1"s Idle Preamble 0 SFD 1 1 0 A4 A3 A0 R4 R3 R0 0 D15 D14 Data Read D1 D0 Idle Z Op Code Write PHY Address Register Address Turn Around 22164A-7 Figure 5. Management Interface - Read Frame Structure MDC MDIO Write 32 "1"s Idle Preamble 0 SFD 1 0 Op Code 1 A4 A3 A0 R4 R3 R0 1 0 D15 D14 D1 D0 PHY Address Register Address Write Turn Around Data Idle 22164A-8 Figure 6. Management Interface - Write Frame Structure 18 Am79C873 PRELIMINARY Register Description Register Address 0 1 2 3 4 5 6 16 17 18 Others Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER DSCR DSCSR 10BTCSR Reserved Basic Mode Control Register Basic Mode Status Register PHY Identifier Register 1 PHY Identifier Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register AMD Specified Configuration Register AMD Specified Configuration/Status Register 10BASE-T Configuration/Status Register Reserved For Future Use-Do Not Read/Write To These Registers Description Key to Default In the register description that follows, the default column takes the form: 1 0 X (Pin No.) Bit set to logic one Bit set to logic zero No default value Value latched in from pin number at reset Am79C873 19 PRELIMINARY Basic Mode Control Register (BMCR) Register 0 Bit Bit Name Default Reset: 1=Software reset 0=Normal operation 0.15 Reset 0, RW/SC When set this bit configures the PHY status and control registers to their default states. This bit will return a value of one until the reset process is complete. Description Loopback: Loopback control register 1=Loopback enabled 0.14 Loopback 0, RW 0=Normal operation When in 100M operation is selected, setting this bit will cause the descrambler to lose synchronization. A 720ms "dead time" will occur before any valid data appears at the MII receive outputs. Speed Select: 1=100 Mbps 0=10 Mbps 0.13 Speed Selection 1, RW Link speed may be selected either by this bit or by Auto-Negotiation if bit 12 of this register is set. When Auto-Negotiation is enabled, this bit will return Auto-Negotiation link speed. Auto-Negotiation Enable: 1= Auto-Negotiation enabled: 0.12 Auto-Negotiation Enable 0= Auto-Negotiation disabled: 1, RW When auto-Negotiation is enabled bits 8 and 13 will contain the AutoNegotiation results. When Auto-Negotiation is disabled bits 8 and 13 will determine the duplex mode and link speed. Power Down: 1=Power Down 0.11 Power Down 0, RW 0=Normal Operation Setting this bit will power down the NetPHY-1 device with the exception of the crystal oscillator circuit. Isolate: 1= Isolate 0= Normal Operation (PHYAD= 0.10 Isolate 00000), RW When this bit is set the data path will be isolated from the MII interface. TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS will be placed in a high impedance state. The management interface is not effected by this bit. When the PHY Address is set to 00000 the isolate bit will be set upon power-up/reset. 20 Am79C873 PRELIMINARY Basic Mode Control Register (BMCR) Register 0 (Continued) Bit Bit Name Default Restart Auto-Negotiation: 1= Restart Auto-Negotiation. 0= Normal Operation 0.9 Restart AutoNegotiation 0, RW/SC When this bit is set the Auto-Negotiation process is re-initiated. When Auto-Negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated. The operation of the AutoNegotiation process will not be affected by the management entity that clears this bit. Duplex Mode: 1= Full Duplex operation. 0.8 Duplex Mode 1, RW 0= Normal operation If Auto-Negotiation is disabled, setting this bit will cause the NetPHY-1 device to operate in Full Duplex mode. When Auto-Negotiation is enabled, this bit reflects the duplex selected by Auto-Negotiation. Collision Test: 1= Collision Test enabled. 0.7 Collision Test 0, RW 0= Normal Operation When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN. 0.6 Reserved 0, RO Reserved: Write as 0, ignore on read. Description Am79C873 21 PRELIMINARY Basic Mode Status Register (BMSR) Register 1 Bit Bit Name Default 100BASE-T4 Capable: 1.15 100BASE-T4 0,RO/P 1=NetPHY-1 device is able to perform in 100BASE-T4 mode. 0=NetPHY-1 device is not able to perform in 100BASE-T4 mode. 100BASE-TX Full Duplex Capable: 1.14 100BASE-TX Full Duplex 1,RO/P 1=NetPHY-1 device is able to perform 100BASE-TX in Full Duplex mode. 0=NetPHY-1 device is not able to perform 100BASE-TX in Full Duplex mode. 100BASE-TX Half Duplex Capable: 1.13 100BASE-TX Half Duplex 1,RO/P 1=NetPHY-1 device is able to perform 100BASE-TX in Half Duplex mode. 0=NetPHY-1 device is not able to perform 100BASE-TX in Half Duplex mode. 10BASE-T Full Duplex Capable: 1,RO/P 1=NetPHY-1 device is able to perform 10BASE-T in Full Duplex mode. 0=NetPHY-1 device is not able to perform 10BASE-T in Full Duplex mode. 10BASE-T Half Duplex Capable: 1,RO/P 1=NetPHY-1 device is able to perform 10BASE-T in Half Duplex mode. 0=NetPHY-1 device is not able to perform 10BASE-T in Half Duplex mode. 0,RO Reserved: Write as 0, ignore on read. MII Frame Preamble Suppression: 1.6 MF Preamble Suppression 0,RO 1=PHY will accept management frames with preamble suppressed. 0=PHY will not accept management frames with preamble suppressed. Auto-Negotiation Complete Auto-Negotiation Complete: 0,RO 1=Auto-Negotiation process completed. 0=Auto-Negotiation process not completed. Remote Fault: 1.4 Remote Fault 0, RO/LH 1= Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is NetPHY-1 device implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set. 0= No remote fault condition detected. Auto-Negotiation Ability Auto Configuration Ability: 1,RO/P 1=NetPHY-1 device able to perform Auto-Negotiation. 0=NetPHY-1 device not able to perform Auto-Negotiation. Link Status: 1=Valid link established (for either 10 Mbps or 100 Mbps operation). 0=Link not established. 1.2 Link Status 0,RO/LL The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the Link Status bit to be cleared and remain cleared until it is read via the management interface. Description 1.12 10BASE-T Full Duplex 1.11 10BASE-T Half Duplex 1.10-1.7 Reserved 1.5 1.3 22 Am79C873 PRELIMINARY Basic Mode Status Register (BMSR) Register 1 Bit Bit Name Default Description Jabber Detect: 1=Jabber condition detected. 1.1 Jabber Detect 0, RO/LH 0=No jabber condition detected. This bit is implemented with a latching function. Once Jabber conditions are detected this bit will remain set until a read operation is completed through a management interface or a NetPHY-1 device reset. This bit works only in 10 Mbps mode. Extended Capability: 1.0 Extended Capability 1,RO/P 1=Extended register capable. 0=Basic register capable only. PHY ID Identifier Register 1 (PHYIDR1) Register 2 The PHY Identifier Registers 1 and 2 work together in a single identifier of the NetPHY-1 device. The Identifier consists of a concatenation of the Organizationally Bit Bit Name Default Unique Identifier (OUI), a vendor's model number, and a model revision number. The IEEE assigned OUI is 00606E. Description OUI Most Significant Bits: 2.15-2.0 OUI_MSB <0181H> This register stores bits 3 - 18 of the OUI (00606E) to bits 15 - 0 of this register, respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2). PHY Identifier Register 2 (PHYIDR2) Register 3 Bit 3.15-3.10 Bit Name OUI_LSB Default OUI Least Significant Bits: <101110>,RO/P Bits 19 - 24 of the OUI (00606E) are mapped to bits 15 - 10 of this register, respectively. Vendor Model Number: 3.9-3.4 VNDR_MDL <000000>,RO/P Six bits of the vendor model number mapped to bits 9 - 4 (most significant bit to bit 9). Model Revision Number: 3.3-3.0 MDL_REV <0001>,RO/P Four bits of the vendor model revision number mapped to bits 3 - 0 (most significant bit to bit 3). Description Am79C873 23 PRELIMINARY Auto-Negotiation Advertisement Register(ANAR) - Register 4 This register contains the advertised abilities of the NetPHY-1 device as they will be transmitted to link partners during Auto-Negotiation. Bit Bit Name Default Next Page Indication: 0=No next page available 4.15 NP 0,RO/P 1=Next page available The NetPHY-1 device does not support the next page function. This bit is permanently set to 0 Acknowledge: 1=Link partner ability data reception acknowledged. 0=Not acknowledged. 4.14 ACK 0,RO The NetPHY-1 device's Auto-Negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the Auto-Negotiation process. Software should not attempt to write to this bit. Remote Fault: 4.13 RF 0, RW 1=Local Device senses a fault condition. 0=No fault detected. 4.12-4.11 Reserved 0, RW Reserved: Write as 0, ignore on read. Flow Control Support: 4.10 FCS 0, RW 1=Controller chip supports flow control ability. 0=Controller chip does not support flow control ability. 100BASE-T4 Support: 1=100BASE-T4 supported by the local device. 4.9 T4 0, RO/P 0=100BASE-T4 not supported. The NetPHY-1 device does not support 100BASE-T4 so this bit is permanently set to 0. 100BASE-TX Full Duplex Support: 4.8 TX_FDX 1, RW 1=100BASE-TX Full Duplex supported by the local device. 0=100BASE-TX Full Duplex not supported. 100BASE-TX Support: 4.7 TX_HDX 1, RW 1=100BASE-TX supported by the local device. 0=100BASE-TX not supported. 10BASE-T Full Duplex Support: 4.6 10_FDX 1, RW 1=10BASE-T Full Duplex supported by the local device. 0=10BASE-T Full Duplex not supported. 10BASE-T Support: 4.5 10_HDX 1, RW 1=10BASE-T supported by the local device. 0=10BASE-T not supported. Protocol Selection Bits: 4.4-4.0 Selector <00001>, RW These bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. Description 24 Am79C873 PRELIMINARY Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5 This register contains the advertised abilities of the link partner as they are received during Auto-Negotiation. Bit Bit Name Default Next Page Indication: 5.15 NP 0, RO 0= Link partner, no next page available. 1= Link partner, next page available. Acknowledge: 1=Link partner ability data reception acknowledged. 5.14 ACK 0, RO 0=Not acknowledged. The NetPHY-1 device's Auto-Negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. Remote Fault: 5.13 RF 0, RO 1=Remote fault indicated by link partner. 0=No remote fault indicated by link partner. 5.12-5.10 Reserved 0, RO Reserved: Write as 0, ignore on read. 100BASE-T4 Support: 5.9 T4 0, RO 1=100BASE-T4 supported by the link partner. 0=100BASE-T4 not supported by the link partner. 100BASE-TX Full Duplex Support: 5.8 TX_FDX 0, RO 1=100BASE-TX Full Duplex supported by the link partner. 0=b 100BASE-TX Full Duplex not supported by the link partner. 100BASE-TX Support: 5.7 TX_HDX 0, RO 1=100BASE-TX Half Duplex supported by the link partner. 0=100BASE-TX Half Duplex not supported by the link partne.r 10BASE-T Full Duplex Support: 5.6 10_FDX 0, RO 1=10BASE-T Full Duplex supported by the link partner. 0=10BASE-T Full Duplex not supported by the link partner. 10BASE-T Support: 5.5 10_HDX 0, RO 1=10BASE-T Half Duplex supported by the link partner. 0=10BASE-T Half Duplex not supported by the link partner. 5.4-5.0 Selector <00000>, RO Protocol Selection Bits: Link partners binary encoded protocol selector. Description Am79C873 25 PRELIMINARY Auto-Negotiation Expansion Register (ANER) - Register 6 Bit 6.15-6.5 Bit Name Reserved Default 0, RO Reserved: Write as 0, ignore on read. Local Device Parallel Detection Fault: 6.4 PDF 0, RO/LH PDF=1: A fault detected via parallel detection function. PDF=0: No fault detected via parallel detection function. Link Partner Next Page Able: 6.3 LP_NP_ABLE 0, RO LP_NP_ABLE=1: Link partner, next page available. LP_NP_ABLE=0: Link partner, no next page. Local Device Next Page Able: 6.2 NP_ABLE 0,RO/P NP_ABLE=1: NetPHY-1 device, next page available. NP_ABLE=0: NetPHY-1 device, no next page. NetPHY-1 device does not support this function, so this bit is always 0. New Page Received: 6.1 PAGE_RX 0, RO/LH A new link code word page received. This bit will be automatically cleared when the register (Register 6) is read by management. Link Partner Auto-Negotiation Able: 6.0 LP_AN_ABLE 0, RO LP_AN_ABLE=1 indicates that the link partner supports AutoNegotiation. Description 26 Am79C873 PRELIMINARY AMD Specified Configuration Register (DSCR) Register 16 Bit Bit Name Default Description Bypass 4B5B Encoding and 5B4B Decoding: 16.15 BP_4B5B , RW 1=4B5B encoder and 5B4B decoder function bypassed. 0=Normal 4B5B and 5B4B operation The value of the pin is latched into this bit at power-up/reset. Bypass Scrambler/Descrambler Function: 16.14 BP_SCR Pin 97, RW 1=Scrambler and descrambler function bypassed. 0=Normal scrambler and descrambler operation. The value of the input pin is latched into this bit at power-up/reset. Bypass Symbol Alignment Function: 1= Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed. 0= Normal operation. The value of the BPALIGN input pin is latched into this bit at power-up/ reset. 16.12 Reserved 0, RW Reserved: This bit must be set as 0. Repeater/Node Mode: 1=Repeater mode. 0=Node mode. 16.11 REPEATER Pin 94, RW In Repeater mode, the Carrier Sense (CRS) output from the NetPHY-1 device will be asserted only by receive activity. In NODE mode, or a mode not configured for Full Duplex operation, CRS will be asserted by either receive or transmit activity. The value of the RPTR/NODE input pin is latched into this bit at power-up reset. 100BASE-TX or FX Mode Control: 16.10 TX 1, RW 1=100BASE-TX operation. 0=100BASE-FX operation. 16.9 UTP 1, RW UTP Cable Control: 1=The media is a UTP cable, 0=STP. CLK25M Disable: 1=CLK25M output clock signal tri-stated. 16.8 CLK25MDIS 0, RW 0=CLK25M enabled. This bit should be set to 1 to disable the 25 MHz output and reduce ground bounce and power consumption. For applications requiring the CLK25M output, set this bit to 0. Force Good Link in 100 Mbps: 16.7 F_LINK_100 1, RW 1=Normal 100 Mbps operation. 0=Force 100 Mbps good link status. This bit is useful for diagnostic purposes. Reserved: 16.6 Reserved 0, RW This bit must be written as 0. 16.13 BP_ALIGN Pin 98, RW Am79C873 27 PRELIMINARY AMD Specified Configuration Register (DSCR) Register 16 Bit Bit Name Default LINKLED Mode Select: 0= Link LED output configured to indicate link status only. 16.5 LINKLED_CTL 0, RW 1= Link LED output configured to indicate traffic status: When the link status is OK, the LED will be on. When the chip is in transmitting or receiving, it flashes. FDXLED Mode Select: 16.4 FDXLED_MODE 0, RW 1= FDXLED output configured to indicate polarity in 10BASE-T mode. 0= FDXLED output configured to indicate Full DuplexFull Duplex mode status for 10 Mbps and 100 Mbps operation. Reset State Machine: 16.3 SMRST 0, RW When this bit is set to 1, all state internal machines will be reset. This bit will clear after reset is completed. MF Preamble Suppression Control: 16.2 MFPSC 0, RW 1= MF preamble suppression on. 0= MF preamble suppression off. MII frame preamble suppression control bi.t Sleep Mode: 16.1 SLEEP 0, RW Writing a 1 to this bit will cause NetPHY-1 device to enter Sleep mode and power down all circuits except the oscillator and clock generator circuit. To exit Sleep mode, write 0 to this bit position. The prior configuration will be retained when the sleep state is terminated, but the state machine will be reset. Remote Loopout Control: 16.0 RLOUT 0, RW When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing. Description 28 Am79C873 PRELIMINARY AMD Specified Configuration and Status Register (DSCSR) - Register 17 Bit Bit Name Default Description 100 M Full Duplex Operation: 17.15 100FDX 1, RO After Auto-Negotiation is completed, the results will be written to this bit. A 1 in this bit position indicates 10 0M Full Duplex operation. The software can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled. 100 M Half Duplex Operation: 17.14 100HDX 1, RO After Auto-Negotiation is completed, the results will be written to this bit. A 1 in this bit position indicates 100 M Half Duplex operation. The software can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled. 10 M Full Duplex Operation: 17.13 10FDX 1, RO After Auto-Negotiation is completed, the results will be written to this bit. A 1 in this bit position indicates 10 M Full Duplex operation. The software can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled. 10 M Half Duplex Operation: 17.12 10HDX 1, RO After Auto-Negotiation is completed, the results will be written to this bit. A 1 in this bit position indicates 10M Half Duplex operation. The software can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled. Reserved: Write as 0, ignore on read. PHY Address Bit 4:0: The values of the PHYAD[4:0] pins are latched to this register at powerup/reset. The first PHY address bit transmitted or received is the MSB (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY. A PHY address of <00000> will cause the isolate bit of the BMCR (bit 10, Register Address 00) to be set. 17.1117.10 Reserved 0, RW 17.8-17.4 PHYAD[4:0] (PHYAD), RW Bit 17.3-17.0 Bit Name ANMB[3:0] Default 0, RO Description Auto-Negotiation Monitor Bits: These bits are for debug only. The Auto-Negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detect signal_link_ready Parallel detect signal_link_ready fail Auto-Negotiation completed successfully Am79C873 29 PRELIMINARY 10BASE-T Configuration/Status (10BTCSRSCR) - Register 18 Bit 18.15 Bit Name Reserved Default 0, RO Reserved: Write as 0, ignore on read. Link Pulse Enable: 18.14 LP_EN 1, RW 1=Transmission of link pulses enabled. 0=Link pulses disabled, good link condition forced. This bit is valid only in 10 Mbps operation. Heartbeat Enable: 1=Heartbeat function enabled. 18.13 HBE Inverse Pin 94, RW 0=Heartbeat function disabled. When the NetPHY-1 device is configured for Full Duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in Full Duplex mode). The initial state of this bit is the inverse value of RPTR/NODE input pin at power on reset. Reserved: Write as 0, ignore on read. Jabber Enable: 1= Jabber function enabled. 18.11 JABEN 1, RW 0= Jabber function disabled. Enables or disables the Jabber function when the NetPHY-1 device is in 10BASE-T Full Duplex or 10BASE-T Transceiver Loop-back mode. 10BASE-T Serial Mode: 1=10BASE-T serial mode selected. 18.10 10BT_SER Pin 98, RW 0=10BASE-T nibble mode selected. The value on the 10BTSER input pin is latched into this bit at power-up/ rese.t Serial mode not supported for 100 Mbps operation. 18.9-18.1 Reserved 0, RO Reserved: Write as 0, ignore on read. Polarity Reversed: 18.0 POLR 0, RO When this bit is set to 1, it indicates that the 10M cable polarity is reversed. This bit is set and cleared by 10BASE-T module automatically. Description 18.12 Reserved 0, RO 30 Am79C873 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . -0C to +70C Supply Voltage with Respect to Ground . . . . . . . . . -4.75 V to +5.25 V DC Input Voltage (VIN) . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage (VOUT) . . . . .-0.5 V to VCC +0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . .0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. Power Consumption 100BASE-TX Full Duplex . . . . . . . . . . . . . . . . 185 mA (Measured using Unscrambled IDLE transmission looped back to RXIN, includes external termination circuitry) 10BASE-T Full Duplex . . . . . . . . . . . . . . . . . . 222 mA (Measured using Maximum packet size, minimum I.P.G. transmission looped back to RXIN, includes external termination circuitry) Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . 165 mA (Measured during Parallel Detect until link established) Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA (Measured with no link established) Power Down Mode . . . . . . . . . . . . . . . . . . . . . 40 mA (Measured while MII Register 0 Bit 11 set true) DC ELECTRICAL CHARACTERISTICS (VCC = 5 VDC, 5%, TA = 0 to 70, unless specified otherwise) Symbol I100TX Parameter Supply Current 100BASE 100BASE-TX active Supply Current 10BASE-TX active I10TTP (Random data, Random IPG and Random size) Supply Current 10BASE-TX active I10TWC IPDM IAN IRST (Max. Packet size, Min. IPG and Worst case data pattern) Supply Current Power Down Mode Supply Current during Auto-Negotiation Supply Current during Reset. Vcc = 5.0 V Vcc = 5.0 V Vcc = 5.0 V Vcc = 5.0 V 220 40 165 115 mA mA mA mA Vcc = 5.0 V 120 mA Conditions Vcc = 5.0 V Min Typical 180 Max 185 Unit mA TTL Inputs (TXD0-TXD3, TX_CLK, MDIO, TX_EN, TX_DV, TX_ER, TESTMODE, PHYAD0-4, OPMODE0-4, RPTR, BPALIGN, BP4B5B, BPSCR, 10BTSER, RESET) VIL VIH IIL IIH Input Low Voltage Input High Voltage Input Low Current Input High Current IIL = -400 uA IIH = 100 uA VIN = 0.4 V VIN = 2.7 V 2.0 -200 100 0.8 V V uA uA Am79C873 31 PRELIMINARY DC ELECTRICAL CHARACTERISTICS (VCC = 5 VDC, 5%, TA = 0 to 70, unless specified otherwise) (Continued) Symbol Parameter Conditions Min Typical Max Unit MII TTL Outputs (RXD0-3, RX_EN, RX_DV, RX_ER, CRS, COL, MDIO) VOL VOH Output Low Voltage Output High Voltage IOL = 4 mA IOH = -4 mA 2.4 0.4 V V Non-MII TTL Outputs (TXLED, RXLED, LINKLED, COLLED, FDXLED, RX_LOCK) VOL VOH VICM Output Low Voltage Output High Voltage RXI+/RXI- Input Common-Mode Voltage IOL = 1 mA IOH = -0.1 mA 2.4 1.5 2.0 2.5 0.4 V V V 100 Termination Across Twisted Pair Transmitter ITD100 100TX+ 100BASE-TX Mode Differential Output Current 10TX 10BASE-T Differential Output Current 19 44 50 21 56 mA mA ITD10 PECL Receiver VIH - VCC PECL Receiver Voltage - High VIL - VCC PECL Receiver Voltage - Low PECL Signal Detect VIH - VCC PECL Signal Detect Voltage - High VIL - VCC PECL Signal Detect Voltage - Low PECL Transmitter VOH VCC VOL VCC PECL Output Voltage - High PECL Output Voltage - Low -1.05 -1.85 -0.88 -1.60 -1.16 -1.81 -0.90 -1.48 -1.16 -1.81 -0.90 -1.48 AC ELECTRICAL CHARACTERISTICS (Over full range of operating conditions unless specified otherwise) Symbol Transmitter tTR/F tTM tTDC tT/T XOST 100TXO+/- Differential Rise/Fall Time 100TXO+/- Differential Rise/Fall Time Mismatch 100TXO+/- Differential Output Duty Cycle Distortion 100TXO+/- Differential Output Peak-toPeak Jitter 100TXO+/- Differential Voltage Overshoot 3.0 -0.5 -0.5 300 5 5.0 0.5 0.5 ns ns ns ps % Parameter Conditions Min Typical Max Unit 32 Am79C873 PRELIMINARY AC ELECTRICAL CHARACTERISTICS (Over full range of operating conditions unless specified otherwise) (Continued) Symbol Parameter Conditions Min Typical Max Unit PECL Transmitter (FX Transmit Interface) ptTR/F ptTM ptTDC ptPPJ ptDDJ 100FXTD+/- Differential Rise/Fall Time 100FXTD+/- Differential Rise/Fall Time Mismatch 100FXTD+/- Differential Output Duty Cycle Distortion 100FXTD+/- Differential Output Peakto-Peak Jitter 100FXTD+/- Differential Output Data Dependent Jitter 1.0 -0.5 -0.5 2.0 0.5 0.5 300 500 ns ns ns ps ps Clock Specifications XNTOL XBTOL tPWH tPWL TX Input Clock Frequency Tolerance TX Output Clock Frequency Tolerance OSC Pulse Width High OSC Pulse Width Low RX_CLK Pulse Width High RX_CLK Pulse Width Low 25 MHz Frequency 25 MHz Frequency -100 14 14 14 14 +100 ppm ppm ns ns ns ns tRPWH tRPWL Am79C873 33 PRELIMINARY MII 100BASE-TX Transmit Timing TX_CLK tTXs TXD [0:3], TX_EN, TX_ER t1 CRS 100TX tTXpd tTXr/f tTXh t2 22164A-9 Figure 7. MII 100BASE-TX Transmit Timing Diagram MII 100BASE-TX Transmit Timing Parameters (Half Duplex) Symbol tTXs tTXh t1 t2 tTXpd tTXr/f Parameter TXD[0:3], TX_EN, TX_ER Setup To TX_CLK High TXD[0:3], TX_EN, TX_ER Hold From TX_CLK High TX_EN Sampled To CRS Asserted TX_EN Sampled To CRS De-asserted TX_EN Sampled To TPO Out (Tx Latency) 100TX Driver Rise/Fall Time 90% To 10%, Into 100 Differential Conditions Min 11 0 3 Typical (Note 1) 4 4 8 4 Max 5 Unit ns ns BT BT BT ns Note: 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing. 34 Am79C873 PRELIMINARY MII 100BASE-TX Receive Timing RX_CLK tTXpd RXD [0:3], RX_DV, RX_ER tRXS tRXh t1 CRS t4 t3 t2 RXI t5 COL 22164A-10 Figure 8. MII 100BASE-TX Receive Timing Diagram MII-100BASE-TX Receive Timing Parameter (Half Duplex) Symbol tRXs tRXh tRXpd t1 t2 t3 t4 t5 Parameter RXD[0:3), RX_DV, RX_ER Setup To RX_CLK High RXD[0:3], RX_DV, RX_ER Hold From RX_CLK High RXI In To RXD[0:3] Out (RX Latency) CRS Asserted To RXD[0:3], RX_DV, RX_ER CRS De-asserted To RXD[0:3], RX_DV, RX_ER RXI In To CRS Asserted RXI Quiet To CRS De-asserted RXI In To COL De-asserted Conditions Min Typical (Note 1) Max Unit 10 10 10 14 14 15 4 0 - 14 18 18 ns ns BT BT BT BT BT BT Note: 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing. Am79C873 35 PRELIMINARY Auto-Negotiation and Fast Link Pulse Timing Clock Pulse Data Pulse Clock Pulse Fast Link Pulses t1 t2 t3 FLP Burst FLP Burst 10TX0 t4 t5 22164A-11 Figure 9. Auto-Negotiation and Fast Link Pulse Timing Diagram Auto-Negotiation and Fast Link Pulse Timing Parameters Symbol t1 t2 t3 t4 t5 Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses Per Burst DATA = 1 Conditions Min 33 Typical 100 62.5 125 2 13.93 33 Max 33 Unit ns us us ms ms ea MII 10BASE-T Nibble Transmit Timing TX_CLK tTXS TXD [0:3], TX_EN, TX_ER t1 CRS tTXpd 10TX tTXh t2 22164A-12 Figure 10. MII 10BASE-T Nibble Transmit Timing Diagram MII-10BASE-T Nibble Transmit Timing Parameters Symbol tTXs tTXh t1 t2 tTXpd Parameter TXD[0:3), TX_EN, TX_ER Setup To TX_CLK High TXD[0:3], TX_EN, TX_ER Hold From TX_CLK High TX_EN Sampled To CRS Asserted TX_EN Sampled To CRS De-asserted TX_EN Sampled To 10TXO Out (Tx Latency) Conditions Min 11 0 Typical 2 15 2 Max 4 20 4 Unit ns ns BT BT BT 36 Am79C873 PRELIMINARY MII 10BASE-T Receive Nibble Timing Diagram RX_CLK tTXpd RXD [0:3], RX_DV, RX_ER t1 CRS t3 RXI t4 t2 tRXS tRXh 22164A-13 Figure 11. MII 10BASE-T Receive Nibble Timing Diagram MII-10BASE-T Receive Nibble Timing Parameters Symbol tRXs tRXh tRXpd t1 t2 t3 t4 Parameter RXD[0:3), RX_DV, RX_ER Setup To RX_CLK High RXD[0:3], RX_DV, RX_ER Hold From RX_CLK High RXI In To RXD[0:3] Out (RX Latency) CRS Asserted To RXD[0:3], RX_DV, RX_ER CRS De-asserted To RXD[0:3], RX_DV, RX_ER RXI In To CRS Asserted RXI Quiet To CRS De-asserted Conditions Min 10 10 1 1 1 Typical 7 14 2 10 Max 20 3 4 15 Unit ns ns BT BT BT BT BT Am79C873 37 PRELIMINARY 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN t1 COL t2 22164A-14 Figure 12. 10BASE-T SQE (Heartbeat) Timing Diagram 10BASE-T SQE (Heartbeat) Timing Parameters Symbol t1 t2 Parameter COL (SQE) Delay After TX_EN Off COL (SQE) Pulse Duration Conditions Min 0.65 0.5 Typical 1.3 1.1 Max 1.6 1.5 Unit ms ms 10BASE-T Jab and Unjab Timing TX_EN t1 TDX COL t2 22164A-15 Figure 13. 10BASE-T Jab and Unjab Timing Diagram 10BASE-T Jab and Unjab Timing Parameters Symbol t1 t2 Parameter Maximum Transmit Time Unjab Time Conditions Min 20 250 Typical 48 505 Max 150 1500 Unit ms ms 38 Am79C873 PRELIMINARY MDIO Timing when OUTPUT by STA MDC 10 ns (Min) t1 MDIO 10 ns (Min) t2 22164A-16 Figure 14. MDIO Timing when OUTPUT by STA Timing Diagram MDIO Timing when OUTPUT by NetPHY-1 Device MDC 0 - 300 ns t3 MDIO 22164A-17 Figure 15. MDIO Timing when OUTPUT by NetPHY-1 Timing Diagram MII Timing Parameters Symbol t1 t2 t3 Parameter MDIO Setup Before MDC MDIO Hold After MDC MDC To MDIO Output Delay Conditions When OUTPUT By STA When OUTPUT By STA When OUTPTU By NetPHY-1 device Min 10 10 0 Typical Max 100 Unit ns ns ns Am79C873 39 PRELIMINARY MAGNETICS SELECTION GUIDE The NetPHY-1 device requires a 1:1 ratio for both the receive and the transmit transformers. Refer to Table 2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics before using them in an application. The transformers listed in Table 2 are electrical equivalent, but may not be pin-to-pin equivalent. CRYSTAL SELECTION GUIDE A crystal can be used to generate the 25 MHz reference clock instead of a crystal oscillator. An M-TRON crystal, part number is 00301-00169, MP-1 Fund, @ 25.000000 MHz, 50 ppm or equivalent may be used. The crystal must be a fundamental type, parallel resonant. Connect to X1 and X2, shunt each crystal lead to ground with an 18pf capacitor (see Figure 16). Table 2. Transformer Requirements Part Number S558-5999-01 LF8200, LF8221 Single Port TG22-3506ND, TD223506G1, TG22-S010ND, 29 30 OSC/XTLB OSCGND X1 X2 32 31 Manufacturer Bel Fuse Delta AGND HALO Electronics, Inc. TG22-S012ND, TG110-S050N2 Quad Port TG110-6506NX, TG110S450NX, TG110-S452NX Y1 25M C18 18 pF AGND C19 18 pF AGND 22164A-18 Nano Pulse Inc. NPI 6181-37, NPI 6120-30, NPI 6120-37 NPI 6170-30 PE-68517, PE-68515, H1019, H1012 ----Single Port Figure 16. Crystal Circuit Diagram Pulse Engineering H1027, H1028 ---- Dual Port PE-69037, H1001, H1036, H1044 ---- Quad Port Valor YCL ST6114, ST6118 20PMT04, 20PMT05 40 Am79C873 PRELIMINARY Table 3. Part List for Example Design Item No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Qty 11 1 4 1 2 1 2 2 1 1 1 1 4 1 4 2 1 1 3 2 3 2 C12 D1,D2,D3,D4 J1 L1,L2 OSC1 Q2,Q1 R1,R2 R3 R4 R5 R6 R7,R8,R14,R15 R9 R10,R11,R12,R13 R17,R16 U1 U2 R17,R18,R21 R19,R21 R22,R23,R26 R24,R25 Reference Number C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C13 Part Description Capacitor, Decoupling, 0.1 f, 50 V Capacitor, .01 f, 2KV LED, General Purpose Connector, RJ45 Ferrite, Panasonic EXCCL4532U Oscillator, Crystal, 25 MHz, 50 ppm Transistor, NNP, General Purpose, 2N2222 Resistor, 470, 5% Resistor, 820, 5% Resistor, 33, 5% Resistor, 510, 5% Resistor, 6.01K, 1% Resistor, 49.9, 1% Resistor, 1.5K, 5% Resistor, 75, 1% Resistor, 10K, 5% NetPHY-1 device, PHY/Transceiver, 100 pin QFP Magnetics, Pulse Engineering, PE68515 Resistor 82, 5% Resistor 62, 5% Resistor 130, 5% Resistor 300, 5% Am79C873 41 PRELIMINARY NetPHY-1 MII Example Schematic VCC VCC R1 VCC VCC RXER RXDV COL CRS RXCLK 220 VCC GND RXD0 RXD1 RXD2 RXD3 R2 1.5K VCC GND MDIO MDC R3 220 TXCLK TXEN VCC GND TXD0 TXD1 TXD2 TXD3 TXER TXLED RXLED LILED GND COLLED# R9 10K U1 74 73 72 79 69 67 64 63 62 59 60 80 78 77 76 75 70 56 54 53 52 66 71 68 65 58 57 55 51 61 C1 10u RXER RXDV RXD0 RXD1 RXD2 RXD3 DGND DGND RXCLK MDC TXCLK TXEN DGND MDIO COLLED# RX_EN CRS GND VCC TXER RXLED LINKLED DVCC TXD1 TXD3 TXD0 TXD2 TXLED COL DVCC GND S1 SW SPST 81 TMODE PHAD0 PHAD1 PHAD2 GND VCC PHAD3 PHAD4 OPMD0 OPMD1 OPMD2 OPMD3 NODEB BPAGN BP45B BPSCR 10SER GND GND 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GND VCC XTLB SD GND RXLOCK SPEED SIGOK GND VCC GND GND GND FDXLED VCC CLK25M RESET# TESTMODE PHYAD0 PHYAD1 PHYAD2 DGND DVCC PHYAD3 PHYAD4 OPMODE0 OPMODE1 OPMODE2 OPMODE3 RPTR/NODE# BPALIGN BP4B5B BPSCR 10BTSER AGND AGND FDXLED# DVCC CLK25M LINKSTS NC DGND RX_LOCK SPEED10 Am79C873 NetPHY-1 UTP TRIDRV DVCC DGND DGND DGND BGRET BGRES AGND AVCC OSC/XTL# AGND VCC 100TXO10TXO+ 10TXOFXRD+ FXSD+ FXRDFXSDAGND AGND AGND AGND AGND AGND AGND AVCC AVCC AVCC AVCC AVCC AVCC AVCC FXTD FXTD RXI+ RXI- 100TXO+ OSCI/X AVCC AVCC R24 130 #12 DM9101F #15 X2 11 12 13 14 15 16 17 1 10 19 18 3 4 6 8 9 30 22 24 25 26 27 28 5 7 20 21 23 29 2 R30 370 FXRD+ FXSD+ FXRD- FXSD- FXTD- TXOM TXOM TXOP TXOP VCC RXIM RXIP GND GND GND GND GND GND GND R2 7 49 .9 1 R2 8 % GND VCC FXSDVCC .1u C18 49 .9 1 % VCC VCC VCC VCC VCC VCC FXTD+ R32 300 R33 62 49.9 1% R34 49.9 1% VCC Y1 25M R29 VCC C16 18P GND GND C16, C17 C17 18P * Load these components or OSC1+ R12. TP15 TP16 R24 82 GND C23 .1u R35 82 R30 130 FXSD+ GND GND FXRD+ R36 82 FXRDC26 FXSD R37 VCC FXT D300 R38 62 HFBR5103T FX1 9 8 7 6 5 4 3 2 1 R39 130 .1u R40 130 TP19 TP17 TP18 FXSD GND FXTD+ FXTDVCC_T VCC_R FXSD FXRDFXRD+ GND 42 Am79C873 PRELIMINARY NetPHY-1 MII Example Schematic (Continued) VCC D1 TXLED D2 RXLED LILED COLLED FDXLED LED LED D6 CLK25M D7 SD RXLOCK SPEED SIGOK LED LED GND LED D9 LED D10 LED D8 RP2 6 5 4 3 2 1 470 TP8 TXD0 #87 C2 .1u #86 #73 #74 C3 .1u #61 #62 C4 .1u #52 #49 C5 .1u #39 #40 C6 .1u #67 TXD3 Digital Ckt Power & Ground Area Locate near U1's VCC & Ground Pins Physically place caps on SOLDER SIDE. D11 Pin 43 (SPEED) LED 100M 820 R19 VCC 75 1 % R17 TP9 GND TP10 CRS R18 75 1% C8 COL #68 C7 .1u TXD1 TXD2 1 2 3 4 5 6 7 8 J2 RJ45 TP4 RXD1 TP3 RXD0 RXDV RXCLK RXER TP5 TP7 TXEN TP6 TXCLK VCC TXER R12 R13 33 R15 33 R16 33 33 R14 33 LED D4 LED D5 LED D3 RP1 1 2 3 4 5 6 470 TP2 MDC RXD3 RXD2 R5 R6 R8 33 33 R7 33 33 R10 R11 33 33 TP1 MDIO R4 33 VCC J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VCC GND VCC MII CON VCC BYPASS CAPACITOR FOR U1 .1u/1KV R20 Q1 510 2N2222 D12 LED 10M 6 Pin 36 (BGRET) Pin 35 (BGRES) R23 5.76K 1% GND RX CKT POWER/GROUND AREA No traces or power near this area R21 5 75 1% 4 3 C9 TP11 .1u TP13 RXIM RXIP 2 1 U2 8 7 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 9 GND 10 11 R22 12 13 14 15 16 TXOM TXOP TP12 TP14 75 1% GND TX CKT POWER/GROUND AREA PE68515 Place caps as close as possible to U1 pins. (SOLDER SIDE) C10 C11 C12 .1u C13 #31 .01u #28 C14 #34 #33 .1u GND VCC SW1 1 2 3 4 5 6 7 8 SW DIP-8 16 15 14 13 12 11 10 9 PHAD0 PHAD1 PHAD2 PHAD3 PHAD4 TMODE XTLB RP3 8 7 6 5 4 3 2 1 RP7_1K .01u #18 .1u #24 #21 #27 VCC Pin 31 (AGND) OSC1 33 R25 8 14 1 7 Place caps close to U1 pins # as shown by number by each cap. Physically place cap on SOLDER SIDE. VCC C19 # 01 GND 10u #100 GND C24 .1u GND VCC_R VCC_T .1u .1u GND C25 10u L1 1uH C27 C28 L2 1uH Advanced Micro Devices Title NetPHY-1 Evaluation Board Size Document Number B netphy1_ev_0 Date: Monday, May 04, 1998 Sheet 1 .1u #6 .01u #11 .1u 1 2 3 4 5 6 7 8 SW DIP-8 GND RP4 SW2 10SER 16 BPSCR BP45B 15 14 BPAGN NODEB 13 12 OPMD3 11 OPMD2 OPMD1 10 9 OPMD0 GND 10 9 8 7 6 5 4 3 2 1 * OUT +VDD 25M NC GND VCC * Do Not Load C20 #7 C21 #8 C22 VCC RP9_1K Rev 2.0 of 1 Am79C873 43 PRELIMINARY PHYSICAL DIMENSIONS* PQR100 HD D 100 1 81 80 F E HE GE 30 31 e GD b 50 51 GD c ~ ~ A2 See Detail F Seating Plane A L L1 0 ~12 A1 Y Detail F *For Reference Only Symbol A A1 A2 b c D E e F GD GE HD HE L L1 y q Trademarks Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. Notes: Dimensions In mm 3.30 Max. 0.10 Min. 2.85 0.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 0.65 0.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max. 0 ~ 12 Dimensions In Inches 0.130 Max. 0.004 Min. 0.1120.005 0.012 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.026 0.006 0.742 NOM. 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.004 Max. 0 ~ 12 1. Dimension D & E do not include resin fins. 2. Dimension GD & GE are for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. NetPHY and PCnet are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 44 Am79C873 |
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